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Date:	Thu, 27 Sep 2001 09:56:57 PDT
From:	"Steven Levine" <steve53@earthlink.net >
Reply-To:	scoug-help@scoug.com
To:	scoug-help@scoug.com
Subject:	SCOUG-Help: What make ram for OS/2?

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In <4.3.2.7.2.20010926095405.00a98550@mail.vcnet.com>, on 09/26/01
at 10:42 AM, Steve Carter said:

>I chose to abandon 72-pin SIMMS altogether and use only 168-pin DIMMs.

Makes sense. Probably saved money too.

>Perhaps Steven Levine would comment on L2 cache size vs cacheable RAM
>and OS/2 memory utilization/organization.

In general, more is better. There are less cache misses. Also, in
general, the closer the cache is to the CPU die, the better it is. Cache
access time is reduced.

How much better depends on your application mix. To see this, turn off
caching in the BIOS and see how slow the box gets. This is similar to
what you would see if every memory access resulted in a cache miss.
Actually, if the cache was enabled and every memory access resulted in a
cache miss, performance would be worse that with no cache at all. That's
because a cache row is wider than the memory bus, so it takes more than
one memory access to fill a row.

The big killers for overall cache performance are cache misses and cache
flushes. Cache misses force memory reads. Cache flushes force memory
writes. Cache flushes are required to ensure multiple bus masters all see
the same data.

The entire subject is very complex. We are talking about probabilities
and patterns. For example, Peter's investing tools make heavy use of
large matrices. The order in which he traverses the indexes will effect
cache performance. The converse is also true. The cache design will have
something to say about what is the best order.

Steven

--
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"Steven Levine" MR2/ICE 2.29d #10183 Warp4/FP11.5
www.scoug.com irc.webbnet.org #scoug (Wed 7pm PST)
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